The present invention pertains to a method and apparatus for page sharing in a multithreaded processor. More particularly, the present invention pertains to the maintenance of a translation look-aside buffer with pre-validation of physical addresses.
As is known in the art, a translation look-aside buffer (TLB) is used to map a virtual memory address to a physical memory address. A programming thread, executed by a processor, initiates a read or update to a physical memory address by providing a virtual address. The processor searches the TLB for the virtual address, retrieves the physical address, and computes the physical address tag for a given cache. The physical address tag for the matching index is retrieved from the cache. A full comparison is executed between the tag of the request and the cache tag. If the cache tag matches the request tag, the search is registered as a hit. If the cache tag does not match the request tag, the search is registered as a miss. The full comparison of the tags and the full retrieval of the physical address from the TLB require a great deal of processor time.
Problems begin to occur when more than one thread is supported in the processor core. Two threads using the same virtual and physical page would require different TLB entries to support different page “access” rights. This defeats the ability to share common memory contents between threads since each thread requires the presence of its own translation entry in the TLB. Thus a request to a line from one thread is unable to get a cache-hit on a line cached by a different thread.